Ikeda Lab.

Award

All
Conference
Journal
Award
Other
  • 飯塚哲也, "時間領域信号処理による高精度・高効率集積回路設計技術に関する研究", 船井情報科学振興財団 第18回船井学術賞, Apr. 2019.
  • 飯塚哲也, 電子情報通信学会 2018年度エレクトロニクスソサイエティ活動功労表彰, Mar. 2019.
  • 飯塚哲也, 2018年東京大学工学部ベストティーチングアワード, Mar. 2019.
  • 飯塚哲也, "高信頼ハードウェアのための高精度磁界計測・解析技術開発", 平成30年度愛知県若手研究者イノベーション創出奨励事業 第13回わかしゃち奨励賞 応用研究部門 最優秀賞, Jan. 2019.
  • 寺尾直樹, 電子情報通信学会エレクトロニクスソサイエティ優秀学生修了表彰, Mar. 2018.
  • 飯塚哲也, "時間モードによる高精度信号処理集積回路の研究", 丸文研究交流財団, 第21回丸文研究奨励賞, Mar. 2018.
  • 織田勇冴, 飯塚哲也, 名倉徹, 浅田邦博, "表面磁界観測による電流推定を用いた集積回路の電源網解析", 情報処理学会 DAシンポジウム2016論文集, DAシンポジウム2016優秀発表学生賞, Aug. 2017.
  • N. N. Mai Khanh, Masahiro SASAKI, and Kunihiro ASADA "A Millimeter-wave Resistorless Pulse Generator with a New On-chip Dipole Patch Antenna in 65-nm CMOS," the 9th IEEE NEWCAS, France, The 3rd place of Best Student Paper Award, Sep. 2011.
  • T. Kikkawa, T. Nakura, and K. Asada "An Automatic Phase Control Circuit with DLL-like Architecture for Phased Array Antenna Systems" Asia Symposium on Quality Electronic Design (ASQED), Kuala Lumpur, Malaysia, Best Paper Award Sep. 2011.
  • Nguyen Ngoc Mai Khanh, M. Sasaki, K. Asada and T. Monma, "A 0.18-μm CMOS Millimeter Wave Pulse Generator with Onchip Antenna and Digitally Programmable Timed Delay Circuit," Asia Symposium on Quality Electronic Design (ASQED), Penang, Malaysia, Best Paper Award, Aug. 2010,
  • Shingo Mandai, Taihei Monma, Toru Nakura, Makoto Ikeda, and Kunihiro Asada, "Multi Functional Range Finder Employing a Dual Imager Core on a Single Chip," In-ternational SoC Design Conference, IEEE CAS Seoul Chapter Best Paper Award(Oral Session), Nov. 2008,
  • T. Iizuka, M. Ikeda, and K. Asada, "Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement," in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 704 -- 707,Dec. 2006,(Best Student Paper Award).
  • T. Iizuka, M. Ikeda, and K. Asada, "Yield-Optimized Standard Cell Layout IP Synthesis System," the 8th IP Award from LSI IP Design Award CommitteesMay. 2006,(IP Award).
  • T. Nakura, M. Ikeda, and K. Asada, "On-chip di/dt Detector IP for Power Supply," IP Based SoC Design Conference & Exhibition (IP-SOC)Dec. 2005,(Best Paper Award).
  • T. Iizuka, M. Ikeda, and K. Asada, "Computational Cost Reduction for Minimum-Width Transistor Placement of Arbitrary Circuit Structures," in Proc. of IPSJ DA Symposium 2005, pp. 121 -- 126,Aug. 2005,(IPSJ Yamashita SIG Research Award).
  • T. Nakura, M. Ikeda, and K. Asada, "On-Chip di/dt Detector Circuit," IEICE Trans. on Electronics,Vol. E88-C, No. 5, pp. 782 -- 787, May. 2005,(IEICE Best Paper Award 2005).
  • T. Nakura, M. Ikeda, and K. Asada, "di/dt Detector Core for Power Supply of LSI," 7th IP Award from LSI IP Design Award CommitteesMay. 2005,(the Outstanding IP Award 2005).
  • T. Iizuka, M. Ikeda, and K. Asada, "Yield-Optimized CMOS Logic Cell Layout IP Synthesis System," 7th IP Award from LSI IP Design Award CommitteesMay. 2005,(Development Promotion).
  • Y. Oike, M. ikeda, and K. Asada, "A High-Speed Associative Processor Using Hierarchical Search Architecture Based on Hamming Distance," 6th IP Award from LSI IP Design Award CommitteesJun. 2004,(the Outstanding IP Award 2004).
  • Y. Oike, M. ikeda, and K. Asada, "Design of Real-Time VGA 3-D Image Sensor Using Mixed-Signal Techniques," IEEE Asia and South Pacific Design Automation Conference (ASP-DAC)Jan.. 2004,(the Best Design Award).
  • Y. Oike, M. ikeda, and K. Asada, "High-Sensitivity and Wide-Dynamic-Range Range Finder With Ambient Light Suppression," 5th IP Award from LSI IP Design Award CommitteesJun. 2003,(IP Award 2003).
  • H. Yamaoka, H. Yoshida, U. Ekinciel, and K. Asada, "A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells," 5th IP Award from LSI IP Design Award CommiteesJun. 2003,(IP Award 2003).
  • H. Yamaoka, H. Yoshida, U. Ekinciel, and K. Asada, "A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells," 4th IP Award from LSI IP Design Award CommiteesJun. 2003,(IP Award 2002).
  • T. Iizuka, M. Ikeda, and K. Asada, "An Exact Algorithm for Practical Routing Problems," in Proc. of IEICE Society Conference 2002, A-3-6, pp. 61, Sep. 2002,(IEICE Young Researcher's Award).
  • Y. Oike, M. ikeda, and K. Asada, "High-Speed Content-Addressable Memory Using Synchronous Hamming Distance Search Circuit," 4th IP Award from LSI IP Design Award CommitteesMay. 2002,(IP Award 2002).
  • Y. Oike, M. Ikeda, and K. Asada, "High-sensitivity and Wide-dynamic-range Position Sensor Using Logarithmic-response and Correlation Circuit," IEEE Int. Conf. on VLSI Design & ASP-DAC (the Best Design Award)", Jan. 2002,